The present invention relates to a semiconductor device and a manufacturing method thereof. The present invention relates particularly to a three-dimensionally mounted semiconductor device and a manufacturing method thereof.
In order to meet the demand for miniaturization of semiconductor devices, multi chip packages have heretofore been used in which a plurality of semiconductor chips are mounted in a single package to enhance packaging densities of the semiconductor devices. As one of them, there is known a three-dimensionally mounted structure wherein a plurality of semiconductor chips are laminated on a wiring board (interposer) in a vertical direction and signals are transmitted via through electrodes respectively provided in the interposer and the respective semiconductor chips. Comparing the three-dimensionally mounted structure provided with the through electrodes and a plane-mounted structure in which a plurality of semiconductor chips are mounted onto a wiring board on a plane basis, a wiring length between the wiring board with the chips mounted thereon and each of the semiconductor chips, and a wiring length between the mutual semiconductor chips can be shortened. It is therefore possible to perform transmission of signals among functional elements formed in the respective semiconductor chips at high speed. Since the wiring board is connectable to a mounting board or printed circuit board via external connecting terminals provided on a surface below the wiring board, wiring lengths for external connection can also be shortened and the transmission of signals to the outside can also be carried out at high speed.
As this type of technique, there has been known a three-dimensionally mounted structure using a semiconductor material for a wiring board as described in, for example, a patent document 1 (Japanese Unexamined Patent Publication No. 2003-110084), which corresponds to U.S. Pat. No. 6,727,582. The wiring board 1 constituted of the semiconductor material includes wirings (L11, L12, L13 and L123) formed in a semiconductor chip mounting surface 1a by a semiconductor process such as photolitho-etching. Thus, wiring widths and wiring pitches can be narrowed as compared with wirings of a wiring board (hereinafter called “insulated board”) unable to utilize the semiconductor process. With the formation of the wiring board 1 and a semiconductor chip 2 by a semiconductor material of the same kind, failures in connection between the wiring board 1 and the semiconductor chip 2, which occur due to the difference in linear expansion coefficient upon heat treatment, can be reduced.
Since, however, a substrate (hereinafter called “mounting board”) with a semiconductor device mounted thereon is not a semiconductor material in general, a wiring board 1 (hereinafter called “semiconductor substrate”) constituted of the semiconductor material and the mounting board 10 differ in linear expansion coefficient from each other when the semiconductor material is used as the wiring board, as in the technique disclosed in the patent document 1. There was a possibility that due to the difference in linear expansion coefficient, failures in connection such as the occurrence of cracks in external connecting terminals 8 connected to the mounting board 10 would occur after mounting upon heat treatment executed upon mounting of the semiconductor device onto the mounting board 10.